1. Field of the Invention
Aspects of the invention relate generally to chemical mechanical polishing and planarization of semiconductor devices and to methods and compositions for removing a barrier layer material by chemical mechanical polishing techniques.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large-scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity for conductors in feature definitions formed in materials having low dielectric constants (low k, defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.
One conductive material gaining acceptance is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), and a higher current carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper diffuses into surrounding material, such as the low k dielectric materials. Barrier layers are deposited in feature definitions formed in the low k dielectric materials prior to copper deposition to reduce or minimize copper diffusion into the surrounding material. Barrier layer materials include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN). Following copper deposition, any excess copper material and excess barrier layer material external to the features formed in the low k dielectric materials is then removed.
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in damascene processes to remove excess deposited material and to provide an even surface for subsequent levels of metallization and processing. Planarization may also be used in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition to effect both chemical activity and mechanical activity.
One approach to polishing barrier materials requires the use of reducing agents that chemically react with the deposited barrier materials and remove the barrier materials from the surface. However, it has been observed that the effectiveness of reducing agents is dependent upon the characteristics of feature definitions formed in a substrate surface. For example, some reducing agents remove barrier materials from unetched portions of the substrate surface (known as the field of the substrate) easily, but often leave behind barrier material residue in features formed in the substrate surface. Residues are undesirable since the residues may detrimentally affect subsequent polishing processes.
One solution to removing barrier layer material residues is to increase the polishing pressure and increase the polishing time to ensure barrier layer removal. However, such a processing condition often results in damage or loss of barrier material at the seam 10 between the barrier layer 15 and the surrounding oxide material 20 forming the copper feature 25, as shown in FIG. 1. Damage to the seam 10 can result in exposing the surrounding oxide to the copper material 30 and result in copper diffusion into the oxide material 20. Additionally, increasing the polishing pressure and increasing the polishing time to ensure barrier layer removal may result in overpolishing the barrier layer and form topographical defects, such as concavities or depressions, referred to as dishing.
FIG. 2 is a schematic view of a substrate illustrating the phenomenon of dishing. Conductive lines 211 and 212 are formed by depositing conductive material, such as copper or copper alloy, over a barrier layer 220 in a feature definition formed in the dielectric layer 210, typically comprised of silicon oxides or other dielectric materials. After overpolishing of the barrier layer, for example, a portion of the conductive material may become depressed by an amount D, referred to as the amount of dishing, forming a concave copper surface. Dishing results in a non-planar surface that impairs the ability to print high resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation. Dishing also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper.
Other reducing agents may be used to remove barrier layer materials with reduced residue; however, such compounds remove the barrier layer materials at relatively low removal rates compared to other reducing agents. The low removal rates increase production times, increase production costs, and reduce substrate throughput. One solution to low removal rates is to increase processing parameters, such as polishing pressure. However, such changes in processing parameters have been observed to result in seam damage.
Therefore, there exists a need for a method and related CMP composition that facilitates the removal of barrier layer materials.